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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/micro/XinLXXW23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gaogang_Xie>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wenjun_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yang_Xu_0010>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yao_Xin>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi_Wang_0004>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FMM.2023.3238012>
foaf:homepage <https://doi.org/10.1109/MM.2023.3238012>
dc:identifier DBLP journals/micro/XinLXXW23 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FMM.2023.3238012 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/micro>
rdfs:label A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gaogang_Xie>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wenjun_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yang_Xu_0010>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yao_Xin>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi_Wang_0004>
swrc:month March - April (xsd:string)
swrc:number 2 (xsd:string)
swrc:pages 110-119 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/micro/XinLXXW23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/micro/XinLXXW23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/micro/micro43.html#XinLXXW23>
rdfs:seeAlso <https://doi.org/10.1109/MM.2023.3238012>
dc:title A Parallel and Updatable Architecture for FPGA-Based Packet Classification With Large-Scale Rule Sets. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 43 (xsd:string)