Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/mj/Maruthamuthu13>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Saravana_Maruthamuthu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1016%2Fj.mejo.2011.07.015>
foaf:homepage	<https://doi.org/10.1016/j.mejo.2011.07.015>
dc:identifier	DBLP journals/mj/Maruthamuthu13 (xsd:string)
dc:identifier	DOI doi.org%2F10.1016%2Fj.mejo.2011.07.015 (xsd:string)
dcterms:issued	2013 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/mj>
rdfs:label	Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Saravana_Maruthamuthu>
swrc:number	1 (xsd:string)
swrc:pages	15-19 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/mj/mj44.html#Maruthamuthu13>
rdfs:seeAlso	<https://doi.org/10.1016/j.mejo.2011.07.015>
dc:title	Ultra low power dual-gate 6T and 8T stack forced CNFET SRAM cells. (xsd:string)
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rdf:type	swrc:Article
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swrc:volume	44 (xsd:string)