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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mj/QiuZXHX19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chun_Jason_Xue>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Keni_Qiu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qirun_Huo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanchao_Xu_0002>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yujie_Zhu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.mejo.2018.11.011>
foaf:homepage <https://doi.org/10.1016/j.mejo.2018.11.011>
dc:identifier DBLP journals/mj/QiuZXHX19 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.mejo.2018.11.011 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mj>
rdfs:label BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chun_Jason_Xue>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Keni_Qiu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qirun_Huo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanchao_Xu_0002>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yujie_Zhu>
swrc:pages 137-146 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mj/QiuZXHX19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mj/QiuZXHX19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mj/mj83.html#QiuZXHX19>
rdfs:seeAlso <https://doi.org/10.1016/j.mejo.2018.11.011>
dc:title BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 83 (xsd:string)