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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mj/SreenivasuluN21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._Bharath_Sreenivasulu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vadthiya_Narendar>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.mejo.2021.105214>
foaf:homepage <https://doi.org/10.1016/j.mejo.2021.105214>
dc:identifier DBLP journals/mj/SreenivasuluN21 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.mejo.2021.105214 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mj>
rdfs:label Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._Bharath_Sreenivasulu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vadthiya_Narendar>
swrc:pages 105214 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mj/SreenivasuluN21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mj/SreenivasuluN21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mj/mj116.html#SreenivasuluN21>
rdfs:seeAlso <https://doi.org/10.1016/j.mejo.2021.105214>
dc:title Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 116 (xsd:string)