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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mj/YangZZTY18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ling_Yang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Manqing_Tan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuelian_Zhang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yude_Yu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.mejo.2018.03.003>
foaf:homepage <https://doi.org/10.1016/j.mejo.2018.03.003>
dc:identifier DBLP journals/mj/YangZZTY18 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.mejo.2018.03.003 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mj>
rdfs:label A high-speed small-area pixel 16‚ÄĮ√ó‚ÄĮ16 ISFET array design using 0.35-őľm CMOS process. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ling_Yang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Manqing_Tan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiang_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuelian_Zhang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yude_Yu>
swrc:pages 107-112 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mj/YangZZTY18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mj/YangZZTY18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mj/mj79.html#YangZZTY18>
rdfs:seeAlso <https://doi.org/10.1016/j.mejo.2018.03.003>
dc:title A high-speed small-area pixel 16‚ÄĮ√ó‚ÄĮ16 ISFET array design using 0.35-őľm CMOS process. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 79 (xsd:string)