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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mr/MartinsVTBB18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eduardo_Augusto_Bezerra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Daniel_Berejuck>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paulo_Ricardo_Cechelero_Villa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rodrigo_Travessini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Victor_M._Goncalves_Martins>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.microrel.2018.01.011>
foaf:homepage <https://doi.org/10.1016/j.microrel.2018.01.011>
dc:identifier DBLP journals/mr/MartinsVTBB18 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.microrel.2018.01.011 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mr>
rdfs:label A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eduardo_Augusto_Bezerra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Marcelo_Daniel_Berejuck>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paulo_Ricardo_Cechelero_Villa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rodrigo_Travessini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Victor_M._Goncalves_Martins>
swrc:pages 50-63 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mr/MartinsVTBB18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mr/MartinsVTBB18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mr/mr83.html#MartinsVTBB18>
rdfs:seeAlso <https://doi.org/10.1016/j.microrel.2018.01.011>
dc:title A dynamic partial reconfiguration design flow for permanent faults mitigation in FPGAs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 83 (xsd:string)