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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mr/StojcevDS04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Goran_Lj._Djordjevic>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mile_K._Stojcev>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tatjana_R._Stankovic>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2FS0026-2714%2803%2900377-9>
foaf:homepage <https://doi.org/10.1016/S0026-2714(03)00377-9>
dc:identifier DBLP journals/mr/StojcevDS04 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2FS0026-2714%2803%2900377-9 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mr>
rdfs:label Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Goran_Lj._Djordjevic>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mile_K._Stojcev>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tatjana_R._Stankovic>
swrc:number 1 (xsd:string)
swrc:pages 173-178 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mr/StojcevDS04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mr/StojcevDS04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mr/mr44.html#StojcevDS04>
rdfs:seeAlso <https://doi.org/10.1016/S0026-2714(03)00377-9>
dc:title Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 44 (xsd:string)