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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/mr/TsaiLYC08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chang-Lin_Yeh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rong-Sheng_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tsung-Yueh_Tsai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yi-Shao_Lai>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1016%2Fj.microrel.2008.01.003>
foaf:homepage <https://doi.org/10.1016/j.microrel.2008.01.003>
dc:identifier DBLP journals/mr/TsaiLYC08 (xsd:string)
dc:identifier DOI doi.org%2F10.1016%2Fj.microrel.2008.01.003 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/mr>
rdfs:label Structural design optimization for board-level drop reliability of wafer-level chip-scale packages. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chang-Lin_Yeh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rong-Sheng_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tsung-Yueh_Tsai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yi-Shao_Lai>
swrc:number 5 (xsd:string)
swrc:pages 757-762 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/mr/TsaiLYC08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/mr/TsaiLYC08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/mr/mr48.html#TsaiLYC08>
rdfs:seeAlso <https://doi.org/10.1016/j.microrel.2008.01.003>
dc:title Structural design optimization for board-level drop reliability of wafer-level chip-scale packages. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 48 (xsd:string)