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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ol/YangVA07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anthony_Vannelli>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shawki_Areibi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhen_Yang_0006>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs11590-006-0027-0>
foaf:homepage <https://doi.org/10.1007/s11590-006-0027-0>
dc:identifier DBLP journals/ol/YangVA07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs11590-006-0027-0 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ol>
rdfs:label An ILP based hierarchical global routing approach for VLSI ASIC design. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anthony_Vannelli>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shawki_Areibi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhen_Yang_0006>
swrc:number 3 (xsd:string)
swrc:pages 281-297 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ol/YangVA07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ol/YangVA07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ol/ol1.html#YangVA07>
rdfs:seeAlso <https://doi.org/10.1007/s11590-006-0027-0>
dc:subject VLSI physical design; Standard cell global routing; Integer Linear Programming (xsd:string)
dc:title An ILP based hierarchical global routing approach for VLSI ASIC design. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 1 (xsd:string)