Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/peerj-cs/ZaganG23>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Ionel_Zagan>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.7717%2Fpeerj-cs.1300>
foaf:homepage	<https://doi.org/10.7717/peerj-cs.1300>
dc:identifier	DBLP journals/peerj-cs/ZaganG23 (xsd:string)
dc:identifier	DOI doi.org%2F10.7717%2Fpeerj-cs.1300 (xsd:string)
dcterms:issued	2023 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/peerj-cs>
rdfs:label	Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Ionel_Zagan>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Vasile_Gheorghita_Gaitan>
swrc:pages	e1300 (xsd:string)
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rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/peerj-cs/peerj-cs9.html#ZaganG23>
rdfs:seeAlso	<https://doi.org/10.7717/peerj-cs.1300>
dc:title	Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation. (xsd:string)
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swrc:volume	9 (xsd:string)