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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/sensors/YuLDL23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Run-Ze_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xi_Deng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhen-Hao_Li>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zheng-Lin_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.3390%2Fs23177498>
foaf:homepage <https://doi.org/10.3390/s23177498>
dc:identifier DBLP journals/sensors/YuLDL23 (xsd:string)
dc:identifier DOI doi.org%2F10.3390%2Fs23177498 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/sensors>
rdfs:label Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Run-Ze_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xi_Deng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhen-Hao_Li>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zheng-Lin_Liu>
swrc:month September (xsd:string)
swrc:number 17 (xsd:string)
swrc:pages 7498 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/sensors/YuLDL23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/sensors/YuLDL23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/sensors/sensors23.html#YuLDL23>
rdfs:seeAlso <https://doi.org/10.3390/s23177498>
dc:title Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 23 (xsd:string)