Fine-grain design space exploration for a cartographic SoC multiprocessor.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/sigarch/BechiniFP03
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https://dblp.l3s.de/d2r/resource/authors/Cosimo_Antonio_Prete
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https://dblp.l3s.de/d2r/resource/authors/Pierfrancesco_Foglia
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2003
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Fine-grain design space exploration for a cartographic SoC multiprocessor.
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85-92
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SoC Multiprocessors, embedded systems, multiprocessor architecture, performance evaluation, trace-driven simulation
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Fine-grain design space exploration for a cartographic SoC multiprocessor.
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