[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/soco/LashevskyS02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rafail_Lashevsky>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yohey_Sato>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs00500-001-0162-6>
foaf:homepage <https://doi.org/10.1007/s00500-001-0162-6>
dc:identifier DBLP journals/soco/LashevskyS02 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs00500-001-0162-6 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/soco>
rdfs:label Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rafail_Lashevsky>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yohey_Sato>
swrc:number 6 (xsd:string)
swrc:pages 462-469 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/soco/LashevskyS02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/soco/LashevskyS02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/soco/soco6.html#LashevskyS02>
rdfs:seeAlso <https://doi.org/10.1007/s00500-001-0162-6>
dc:subject ?MOS transistor, Artificial neural networks, Analog hardware implementation, Deviation tolerance (xsd:string)
dc:title Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)