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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/sttt/GaravelVZ01>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9sar_Viho>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hubert_Garavel>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Massimo_Zendri>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs100090100044>
foaf:homepage <https://doi.org/10.1007/s100090100044>
dc:identifier DBLP journals/sttt/GaravelVZ01 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs100090100044 (xsd:string)
dcterms:issued 2001 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/sttt>
rdfs:label System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9sar_Viho>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hubert_Garavel>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Massimo_Zendri>
swrc:number 3 (xsd:string)
swrc:pages 314-331 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/sttt/GaravelVZ01/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/sttt/GaravelVZ01>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/sttt/sttt3.html#GaravelVZ01>
rdfs:seeAlso <https://doi.org/10.1007/s100090100044>
dc:subject Cache coherency; cc-numa; Code generation; Co-design; Computer architecture; Conformance testing; Co-simulation; Formal methods; Formal specification; Hardware design; lotos; Process algebra; numa; Rapid prototyping; System level design; Test generation; Testing; Validation; Verification (xsd:string)
dc:title System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 3 (xsd:string)