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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/sttt/VasudevanEA07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/E._Allen_Emerson>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jacob_A._Abraham>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shobha_Vasudevan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10009-006-0022-x>
foaf:homepage <https://doi.org/10.1007/s10009-006-0022-x>
dc:identifier DBLP journals/sttt/VasudevanEA07 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10009-006-0022-x (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/sttt>
rdfs:label Improved verification of hardware designs through antecedent conditioned slicing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/E._Allen_Emerson>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jacob_A._Abraham>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shobha_Vasudevan>
swrc:number 1 (xsd:string)
swrc:pages 89-101 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/sttt/VasudevanEA07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/sttt/VasudevanEA07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/sttt/sttt9.html#VasudevanEA07>
rdfs:seeAlso <https://doi.org/10.1007/s10009-006-0022-x>
dc:subject Hardware verification; Model checking; Program slicing; LTL property; Antecedent conditioned slicing; Hardware description languages; Verilog RTL (xsd:string)
dc:title Improved verification of hardware designs through antecedent conditioned slicing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 9 (xsd:string)