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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/taco/CezeSTTR06>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/James_Tuck_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jose_Renau>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Josep_Torrellas>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Karin_Strauss>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Luis_Ceze>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1138035.1138038>
foaf:homepage <https://doi.org/10.1145/1138035.1138038>
dc:identifier DBLP journals/taco/CezeSTTR06 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1138035.1138038 (xsd:string)
dcterms:issued 2006 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/taco>
rdfs:label CAVA: Using checkpoint-assisted value prediction to hide L2 misses. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/James_Tuck_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jose_Renau>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Josep_Torrellas>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Karin_Strauss>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Luis_Ceze>
swrc:number 2 (xsd:string)
swrc:pages 182-208 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/taco/CezeSTTR06/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/taco/CezeSTTR06>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/taco/taco3.html#CezeSTTR06>
rdfs:seeAlso <https://doi.org/10.1145/1138035.1138038>
dc:subject Value prediction, checkpointed processor architectures, memory hierarchies, multiprocessor (xsd:string)
dc:title CAVA: Using checkpoint-assisted value prediction to hide L2 misses. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 3 (xsd:string)