Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/taco/MaratheMS06
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DOI doi.org%2F10.1145%2F1187976.1187978
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2006
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Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques.
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4
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390-423
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dc:
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Hardware performance monitoring, SMPs, cache analysis, coherence protocols, dynamic binary rewriting, program instrumentation
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Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques.
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