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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/taco/SantanaRLV04>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alex_Ram%E2%88%9A%E2%89%A0rez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Josep_Llu%E2%88%9A%E2%89%A0s_Larriba-Pey>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mateo_Valero>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Oliverio_J._Santana>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1145%2F1011528.1011532>
foaf:homepage <https://doi.org/10.1145/1011528.1011532>
dc:identifier DBLP journals/taco/SantanaRLV04 (xsd:string)
dc:identifier DOI doi.org%2F10.1145%2F1011528.1011532 (xsd:string)
dcterms:issued 2004 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/taco>
rdfs:label A low-complexity fetch architecture for high-performance superscalar processors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alex_Ram%E2%88%9A%E2%89%A0rez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Josep_Llu%E2%88%9A%E2%89%A0s_Larriba-Pey>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mateo_Valero>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Oliverio_J._Santana>
swrc:number 2 (xsd:string)
swrc:pages 220-245 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/taco/SantanaRLV04/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/taco/SantanaRLV04>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/taco/taco1.html#SantanaRLV04>
rdfs:seeAlso <https://doi.org/10.1145/1011528.1011532>
dc:subject Branch prediction, fetch architecture, high performance, instruction stream, low complexity (xsd:string)
dc:title A low-complexity fetch architecture for high-performance superscalar processors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 1 (xsd:string)