Inter-cluster communication in VLIW architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/taco/TerechkoC07
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/taco/TerechkoC07
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Andrei_Sergeevich_Terechko
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Henk_Corporaal
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homepage
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http://dx.doi.org/doi.org%2F10.1145%2F1250727.1250731
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foaf:
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DBLP journals/taco/TerechkoC07
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dc:
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DOI doi.org%2F10.1145%2F1250727.1250731
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dcterms:
issued
2007
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rdfs:
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Inter-cluster communication in VLIW architectures.
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https://dblp.l3s.de/d2r/resource/authors/Andrei_Sergeevich_Terechko
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swrc:
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2
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swrc:
pages
11
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rdfs:
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rdfs:
seeAlso
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dc:
subject
Instruction-level parallelism, VLIW, clock frequency, cluster assignment, instruction scheduler, intercluster communication, optimizing compiler, pipelining, register allocation
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dc:
title
Inter-cluster communication in VLIW architectures.
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4
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