VLIW instruction scheduling for minimal power variation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/taco/XiaoL07
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dc:
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Shu_Xiao_0001
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http://dx.doi.org/doi.org%2F10.1145%2F1275937.1275942
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2007
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VLIW instruction scheduling for minimal power variation.
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dc:
subject
Instruction scheduling, VLIW processors, power variation reduction
(xsd:string)
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title
VLIW instruction scheduling for minimal power variation.
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