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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/AsariE94>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C._Eswaran>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/K._Vijayan_Asari>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.250617>
foaf:homepage <https://doi.org/10.1109/12.250617>
dc:identifier DBLP journals/tc/AsariE94 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.250617 (xsd:string)
dcterms:issued 1994 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label An Optimization Technique for the Design of Multiple Valued PLA's. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C._Eswaran>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/K._Vijayan_Asari>
swrc:number 1 (xsd:string)
swrc:pages 118-122 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/AsariE94/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/AsariE94>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc43.html#AsariE94>
rdfs:seeAlso <https://doi.org/10.1109/12.250617>
dc:subject logic arrays; minimisation; encoding; adders; many-valued logics; network synthesis; optimization technique; multiple valued PLA design; output encoding; binary output; multiple function literal circuits; minimization; PLA size; programmable logic arrays; adder; multiple valued logic. (xsd:string)
dc:title An Optimization Technique for the Design of Multiple Valued PLA's. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 43 (xsd:string)