Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/BajwaOI94
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Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
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VLSI; parallel architectures; performance evaluation; area time trade-offs; micro-grain VLSI array architectures; performance; massively parallel control-flow architectures; associative memory architecture; Mux-based SIMD architecture; RAMs; systolic MIMD/MISD computation; data-flow requirements; FFT; matrix multiplication.
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Area Time Trade-Offs in Micro-Grain VLSI Array Architectures.
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