Efficient Testing of Optimal Time Adders.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/Becker88
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Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/Becker88
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Bernd_Becker_0001
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2F12.2262
>
foaf:
homepage
<
https://doi.org/10.1109/12.2262
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dc:
identifier
DBLP journals/tc/Becker88
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2F12.2262
(xsd:string)
dcterms:
issued
1988
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tc
>
rdfs:
label
Efficient Testing of Optimal Time Adders.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Bernd_Becker_0001
>
swrc:
number
9
(xsd:string)
swrc:
pages
1113-1121
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tc/Becker88/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tc/Becker88
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tc/tc37.html#Becker88
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rdfs:
seeAlso
<
https://doi.org/10.1109/12.2262
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dc:
subject
optimal time adders; carry look-ahead adder; conditional sum adder; VLSI chip; adders; integrated logic circuits; logic testing; VLSI.
(xsd:string)
dc:
title
Efficient Testing of Optimal Time Adders.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
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rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
37
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