Via Assignment in Single-Row Routing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/BhaskerS89
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/BhaskerS89
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dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Jayaram_Bhasker
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Sartaj_Sahni
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foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2F12.8737
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foaf:
homepage
<
https://doi.org/10.1109/12.8737
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dc:
identifier
DBLP journals/tc/BhaskerS89
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dc:
identifier
DOI doi.org%2F10.1109%2F12.8737
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dcterms:
issued
1989
(xsd:gYear)
swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/tc
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rdfs:
label
Via Assignment in Single-Row Routing.
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foaf:
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<
https://dblp.l3s.de/d2r/resource/authors/Jayaram_Bhasker
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foaf:
maker
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https://dblp.l3s.de/d2r/resource/authors/Sartaj_Sahni
>
swrc:
number
1
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swrc:
pages
142-149
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owl:
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http://bibsonomy.org/uri/bibtexkey/journals/tc/BhaskerS89/dblp
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owl:
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http://dblp.rkbexplorer.com/id/journals/tc/BhaskerS89
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rdfs:
seeAlso
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http://dblp.uni-trier.de/db/journals/tc/tc38.html#BhaskerS89
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rdfs:
seeAlso
<
https://doi.org/10.1109/12.8737
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dc:
subject
multilayer PCB; via assignment; single-row routing; interconnection; complexity results; heuristics; circuit layout CAD; computational complexity; printed circuit design.
(xsd:string)
dc:
title
Via Assignment in Single-Row Routing.
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volume
38
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