An Architecture for Bitonic Sorting with Optimal VLSI Performance.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/BilardiP84
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https://dblp.l3s.de/d2r/resource/authors/Gianfranco_Bilardi
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http://dx.doi.org/doi.org%2F10.1109%2FTC.1984.5009338
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1984
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An Architecture for Bitonic Sorting with Optimal VLSI Performance.
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dc:
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An Architecture for Bitonic Sorting with Optimal VLSI Performance.
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