Deriving Logic Systems for Path Delay Test Generation.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/BoseAA98
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https://dblp.l3s.de/d2r/resource/authors/Prathima_Agrawal
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https://dblp.l3s.de/d2r/resource/authors/Soumitra_Bose
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https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal
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DBLP journals/tc/BoseAA98
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1998
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Deriving Logic Systems for Path Delay Test Generation.
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8
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829-846
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dc:
subject
Delay testing, digital test, multivalued logic, path delay faults, simulation, timing analysis.
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Deriving Logic Systems for Path Delay Test Generation.
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47
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