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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/BoseAA98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Prathima_Agrawal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Soumitra_Bose>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.707585>
foaf:homepage <https://doi.org/10.1109/12.707585>
dc:identifier DBLP journals/tc/BoseAA98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.707585 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Deriving Logic Systems for Path Delay Test Generation. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Prathima_Agrawal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Soumitra_Bose>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vishwani_D._Agrawal>
swrc:number 8 (xsd:string)
swrc:pages 829-846 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/BoseAA98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/BoseAA98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc47.html#BoseAA98>
rdfs:seeAlso <https://doi.org/10.1109/12.707585>
dc:subject Delay testing, digital test, multivalued logic, path delay faults, simulation, timing analysis. (xsd:string)
dc:title Deriving Logic Systems for Path Delay Test Generation. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 47 (xsd:string)