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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/ChessL98>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Brian_Chess>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tracy_Larrabee>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.660170>
foaf:homepage <https://doi.org/10.1109/12.660170>
dc:identifier DBLP journals/tc/ChessL98 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.660170 (xsd:string)
dcterms:issued 1998 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Logic Testing of Bridging Faults in CMOS Integrated Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Brian_Chess>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tracy_Larrabee>
swrc:number 3 (xsd:string)
swrc:pages 338-345 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/ChessL98/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/ChessL98>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc47.html#ChessL98>
rdfs:seeAlso <https://doi.org/10.1109/12.660170>
dc:subject Bridging faults, fault simulation, test pattern generation, realistic faults, fault models. (xsd:string)
dc:title Logic Testing of Bridging Faults in CMOS Integrated Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 47 (xsd:string)