An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/ChoiPK90
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https://dblp.l3s.de/d2r/resource/authors/Kyu_Ho_Park
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1990
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An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems.
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3
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404-407
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dc:
subject
fault-tolerant clock synchronization algorithm; large multiprocessor systems; malicious faults; reference clock selection; lower gate complexity; smaller time delay; sorter; counting encoder; threshold generation logic; programmable registers; gate complexity; fault tolerant computing; multiprocessing systems; synchronisation.
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An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems.
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39
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