Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/CodrescuWM01
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https://dblp.l3s.de/d2r/resource/authors/D._Scott_Wills
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https://dblp.l3s.de/d2r/resource/authors/James_D._Meindl
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https://dblp.l3s.de/d2r/resource/authors/Lucian_Codrescu
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DBLP journals/tc/CodrescuWM01
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2001
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Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
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swrc:
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1
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swrc:
pages
67-82
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dc:
subject
Thread speculation, multithreading, value prediction, multiscalar, chip-multiprocessor, parallelization.
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dc:
title
Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications.
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50
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