A High Data-Rate Digital Output Correlator Design. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/K._Wayne_Current>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTC.1980.1675592>
foaf:homepage	<https://doi.org/10.1109/TC.1980.1675592>
dc:identifier	DBLP journals/tc/Current80b (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FTC.1980.1675592 (xsd:string)
dcterms:issued	1980 (xsd:gYear)
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rdfs:label	A High Data-Rate Digital Output Correlator Design. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/K._Wayne_Current>
swrc:number	5 (xsd:string)
swrc:pages	403-405 (xsd:string)
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rdfs:seeAlso	<https://doi.org/10.1109/TC.1980.1675592>
dc:subject	threshold logic, Digital correlators, latched quaternary threshold logic full adders, multiple valued logic, parallel counters (xsd:string)
dc:title	A High Data-Rate Digital Output Correlator Design. (xsd:string)
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swrc:volume	29 (xsd:string)