Clock Skew Optimization.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/Fishburn90
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/Fishburn90
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2F12.55696
>
foaf:
homepage
<
https://doi.org/10.1109/12.55696
>
dc:
identifier
DBLP journals/tc/Fishburn90
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1109%2F12.55696
(xsd:string)
dcterms:
issued
1990
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/tc
>
rdfs:
label
Clock Skew Optimization.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/John_P._Fishburn
>
swrc:
number
7
(xsd:string)
swrc:
pages
945-951
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/tc/Fishburn90/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/tc/Fishburn90
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/tc/tc39.html#Fishburn90
>
rdfs:
seeAlso
<
https://doi.org/10.1109/12.55696
>
dc:
subject
performance; synchronous digital system; path delays; clock signal; flip-flops; linear programs; minimum safety margin; circuit simulation; CMOS; circuit analysis computing; CMOS integrated circuits; optimisation.
(xsd:string)
dc:
title
Clock Skew Optimization.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
39
(xsd:string)