Hypergraph Coloring and Reconfigured RAM Testing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/FranklinS94
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/FranklinS94
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Kewal_K._Saluja
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Manoj_Franklin
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2F12.286305
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foaf:
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dc:
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DBLP journals/tc/FranklinS94
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dc:
identifier
DOI doi.org%2F10.1109%2F12.286305
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dcterms:
issued
1994
(xsd:gYear)
swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/tc
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rdfs:
label
Hypergraph Coloring and Reconfigured RAM Testing.
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<
https://dblp.l3s.de/d2r/resource/authors/Kewal_K._Saluja
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https://dblp.l3s.de/d2r/resource/authors/Manoj_Franklin
>
swrc:
number
6
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swrc:
pages
725-736
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http://bibsonomy.org/uri/bibtexkey/journals/tc/FranklinS94/dblp
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rdfs:
seeAlso
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seeAlso
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dc:
subject
graph colouring; redundancy; DRAM chips; integrated memory circuits; computational complexity; random-access storage; reconfigurable architectures; logic testing; hypergraph coloring; reconfigured RAM testing; RAM decoders; silicon area; critical path lengths; memory chips; physical neighborhood pattern sensitive faults; test algorithms; test lengths; reconfigured DRAMs; stuck-at faults; decoder faults.
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dc:
title
Hypergraph Coloring and Reconfigured RAM Testing.
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volume
43
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