An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/Giraud06
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/Giraud06
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Christophe_Giraud_0001
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foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1109%2FTC.2006.135
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DBLP journals/tc/Giraud06
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DOI doi.org%2F10.1109%2FTC.2006.135
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dcterms:
issued
2006
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swrc:
journal
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rdfs:
label
An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis.
(xsd:string)
foaf:
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https://dblp.l3s.de/d2r/resource/authors/Christophe_Giraud_0001
>
swrc:
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9
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swrc:
pages
1116-1120
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rdfs:
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http://dblp.uni-trier.de/db/journals/tc/tc55.html#Giraud06
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rdfs:
seeAlso
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https://doi.org/10.1109/TC.2006.135
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dc:
subject
Smart cards, side channel, fault injection, simple power analysis, public-key cryptosystems, RSA, exponentiation.
(xsd:string)
dc:
title
An RSA Implementation Resistant to Fault Attacks and to Simple Power Analysis.
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swrc:Article
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55
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