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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/HoritaT00>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.862214>
foaf:homepage <https://doi.org/10.1109/12.862214>
dc:identifier DBLP journals/tc/HoritaT00 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.862214 (xsd:string)
dcterms:issued 2000 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Fault-Tolerant Processor Arrays Based on the 1¬Ĺ-Track Switches with Flexible Spare Distributions. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Itsuo_Takanami>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tadayoshi_Horita>
swrc:number 6 (xsd:string)
swrc:pages 542-552 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/HoritaT00/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/HoritaT00>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc49.html#HoritaT00>
rdfs:seeAlso <https://doi.org/10.1109/12.862214>
dc:subject The 1$frac{1}{2}$-track switch model, mesh-connected processor arrays, reconfiguration, wafer scale integration, yield enhancement. (xsd:string)
dc:title Fault-Tolerant Processor Arrays Based on the 1¬Ĺ-Track Switches with Flexible Spare Distributions. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 49 (xsd:string)