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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/HosseinabadySLN08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Lombardi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Hosseinabady>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shervin_Sharifi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.70806>
foaf:homepage <https://doi.org/10.1109/TC.2007.70806>
dc:identifier DBLP journals/tc/HosseinabadySLN08 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2007.70806 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label A Selective Trigger Scan Architecture for VLSI Testing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fabrizio_Lombardi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mohammad_Hosseinabady>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shervin_Sharifi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zainalabedin_Navabi>
swrc:number 3 (xsd:string)
swrc:pages 316-328 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/HosseinabadySLN08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/HosseinabadySLN08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc57.html#HosseinabadySLN08>
rdfs:seeAlso <https://doi.org/10.1109/TC.2007.70806>
dc:subject Scan Test, Test Data Volume, Test Application Time, Test Power, Test Compression, Delay Testing (xsd:string)
dc:title A Selective Trigger Scan Architecture for VLSI Testing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 57 (xsd:string)