A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/HsuG96
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https://dblp.l3s.de/d2r/resource/authors/Yuan-Chieh_Hsu
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1996
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A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.
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11
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1312-1318
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dc:
subject
Delay testing, robust path delay testing, at-speed delay testing, fault simulation.
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title
A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits.
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