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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/HuaLP93>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jih-Kwon_Peir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kien_A._Hua>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lishing_Liu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2F12.241604>
foaf:homepage <https://doi.org/10.1109/12.241604>
dc:identifier DBLP journals/tc/HuaLP93 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2F12.241604 (xsd:string)
dcterms:issued 1993 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Designing High-Performance Processors Using Real Address Prediction. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jih-Kwon_Peir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kien_A._Hua>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lishing_Liu>
swrc:number 9 (xsd:string)
swrc:pages 1146-1151 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/HuaLP93/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/HuaLP93>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc42.html#HuaLP93>
rdfs:seeAlso <https://doi.org/10.1109/12.241604>
dc:subject high-performance processors; real address prediction; cache access path; shorter cycle time; pipeline stages; prediction methods; address translation; buffer storage; pipeline processing. (xsd:string)
dc:title Designing High-Performance Processors Using Real Address Prediction. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)