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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/JigangSW07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Thambipillai_Srikanthan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wu_Jigang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaodong_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2007.1085>
foaf:homepage <https://doi.org/10.1109/TC.2007.1085>
dc:identifier DBLP journals/tc/JigangSW07 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2007.1085 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Thambipillai_Srikanthan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wu_Jigang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaodong_Wang>
swrc:number 10 (xsd:string)
swrc:pages 1387-1400 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/JigangSW07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/JigangSW07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc56.html#JigangSW07>
rdfs:seeAlso <https://doi.org/10.1109/TC.2007.1085>
dc:subject Degradable VLSI array, reconfiguration, faulttolerance, algorithm, routing (xsd:string)
dc:title Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 56 (xsd:string)