High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/KawahitoINKH94
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High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
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dc:
subject
VLSI; multiplying circuits; multiplier design; multiple-valued current-mode circuits; VLSI; high-speed multiplier; carry-propagation-free addition trees; multiple-valued current-mode; carry-propagation-free addition; number representations; area efficient design; redundant number representations; tree structure.
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High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
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