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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/KhanK10>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Omer_Khan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sandip_Kundu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.2009.76>
foaf:homepage <https://doi.org/10.1109/TC.2009.76>
dc:identifier DBLP journals/tc/KhanK10 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.2009.76 (xsd:string)
dcterms:issued 2010 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Omer_Khan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sandip_Kundu>
swrc:number 5 (xsd:string)
swrc:pages 651-665 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/KhanK10/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/KhanK10>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc59.html#KhanK10>
rdfs:seeAlso <https://doi.org/10.1109/TC.2009.76>
dc:subject Chip multiprocessor (CMP), hard-error tolerance, hardware/software codesign, hypervisor, virtualization. (xsd:string)
dc:title Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 59 (xsd:string)