Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/KhanK10
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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.
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Chip multiprocessor (CMP), hard-error tolerance, hardware/software codesign, hypervisor, virtualization.
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Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors.
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