The Organization of Permutation Architectures with Bused Interconnections.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/KilianKL90
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Charles_E._Leiserson
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Joe_Kilian
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Shlomo_Kipnis
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http://dx.doi.org/doi.org%2F10.1109%2F12.61044
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DBLP journals/tc/KilianKL90
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DOI doi.org%2F10.1109%2F12.61044
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dcterms:
issued
1990
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The Organization of Permutation Architectures with Bused Interconnections.
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https://dblp.l3s.de/d2r/resource/authors/Charles_E._Leiserson
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foaf:
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https://dblp.l3s.de/d2r/resource/authors/Shlomo_Kipnis
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swrc:
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11
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swrc:
pages
1346-1358
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dc:
subject
permutation architectures; bused interconnections; VLSI chips; abelian; combinatorial notion; multiprocessor interconnection networks.
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The Organization of Permutation Architectures with Bused Interconnections.
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39
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