Incorporating Yield Enhancement into the Floorplanning Process.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/KorenK00
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2000
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Incorporating Yield Enhancement into the Floorplanning Process.
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dc:
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Floorplanning, memory ICs, microprocessor, redundancy, routing complexity, yield.
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title
Incorporating Yield Enhancement into the Floorplanning Process.
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