On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/KumarT91
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DBLP journals/tc/KumarT91
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1991
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On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication.
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6
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770-774
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dc:
subject
optimal family of linear systolic arrays; matrix multiplication; local storage; processing elements; delay; fault wafer scale integration models; circuit layout CAD; systolic arrays; VLSI.
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On Synthesizing Optimal Family of Linear Systolic Arrays for Matrix Multiplication.
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