Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/LinderH96
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bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/LinderH96
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https://dblp.l3s.de/d2r/resource/authors/James_C._Harden
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http://dx.doi.org/doi.org%2F10.1109%2F12.537126
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DBLP journals/tc/LinderH96
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1996
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Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry.
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https://dblp.l3s.de/d2r/resource/authors/Daniel_H._Linder
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9
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1031-1044
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dc:
subject
Asynchronous circuitry, data flow, delay-insensitive circuitry, dual-rail encoding, LEDR, marked graphs, phased logic, synchronous circuitry.
(xsd:string)
dc:
title
Phased Logic Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry.
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