Architecture for VLSI Design of Reed-Solomon Decoders. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/tc/Liu84>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Kuang_Yung_Liu>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1109%2FTC.1984.1676409>
foaf:homepage	<https://doi.org/10.1109/TC.1984.1676409>
dc:identifier	DBLP journals/tc/Liu84 (xsd:string)
dc:identifier	DOI doi.org%2F10.1109%2FTC.1984.1676409 (xsd:string)
dcterms:issued	1984 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label	Architecture for VLSI Design of Reed-Solomon Decoders. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Kuang_Yung_Liu>
swrc:number	2 (xsd:string)
swrc:pages	178-189 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/tc/Liu84/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/journals/tc/Liu84>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/tc/tc33.html#Liu84>
rdfs:seeAlso	<https://doi.org/10.1109/TC.1984.1676409>
dc:subject	VLSI, BCH decoders, error-correcting codes, finite field processors, parallel processing, pipeline processing, Reed?Solomon decoders (xsd:string)
dc:title	Architecture for VLSI Design of Reed-Solomon Decoders. (xsd:string)
dc:type	<http://purl.org/dc/dcmitype/Text>
rdf:type	swrc:Article
rdf:type	foaf:Document
swrc:volume	33 (xsd:string)