Variable Instruction Set Architecture and Its Compiler Support.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/LiuCKR03
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dcterms:
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/LiuCKR03
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https://dblp.l3s.de/d2r/resource/authors/Jack_Liu
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https://dblp.l3s.de/d2r/resource/authors/Rupan_Roy
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https://dblp.l3s.de/d2r/resource/authors/Timothy_Kong
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DBLP journals/tc/LiuCKR03
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DOI doi.org%2F10.1109%2FTC.2003.1214337
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2003
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rdfs:
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Variable Instruction Set Architecture and Its Compiler Support.
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https://dblp.l3s.de/d2r/resource/authors/Fred_C._Chow
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7
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881-895
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dc:
subject
Configurable code generation, dictionary, embedded processor, enumeration, instruction scheduling, program representation, resource modeling, variable instruction set.
(xsd:string)
dc:
title
Variable Instruction Set Architecture and Its Compiler Support.
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52
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