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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/tc/LiuY83>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Philip_S._Liu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tzay_Y._Young>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1109%2FTC.1983.1676177>
foaf:homepage <https://doi.org/10.1109/TC.1983.1676177>
dc:identifier DBLP journals/tc/LiuY83 (xsd:string)
dc:identifier DOI doi.org%2F10.1109%2FTC.1983.1676177 (xsd:string)
dcterms:issued 1983 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/tc>
rdfs:label VLSI Array Design Under Constraint of Limited I/O Bandwidth. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Philip_S._Liu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tzay_Y._Young>
swrc:number 12 (xsd:string)
swrc:pages 1160-1170 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/tc/LiuY83/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/tc/LiuY83>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/tc/tc32.html#LiuY83>
rdfs:seeAlso <https://doi.org/10.1109/TC.1983.1676177>
dc:subject VLSI implementation, Design constraints, image processing, matrix inversion array, multiplication array, performance analysis, reconfigurable VLSI array, signal processing, VLSI architecture (xsd:string)
dc:title VLSI Array Design Under Constraint of Limited I/O Bandwidth. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 32 (xsd:string)