A Highly Regular and Scalable AES Hardware Architecture.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/MangardAD03
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/MangardAD03
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Manfred_Josef_Aigner
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Sandra_Dominikus
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Stefan_Mangard
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2FTC.2003.1190589
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homepage
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DBLP journals/tc/MangardAD03
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DOI doi.org%2F10.1109%2FTC.2003.1190589
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dcterms:
issued
2003
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swrc:
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rdfs:
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A Highly Regular and Scalable AES Hardware Architecture.
(xsd:string)
foaf:
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https://dblp.l3s.de/d2r/resource/authors/Manfred_Josef_Aigner
>
foaf:
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https://dblp.l3s.de/d2r/resource/authors/Sandra_Dominikus
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https://dblp.l3s.de/d2r/resource/authors/Stefan_Mangard
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swrc:
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4
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swrc:
pages
483-491
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rdfs:
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dc:
subject
Advanced Encryption Standard (AES), hardware architecture, IP module, VLSI, scalability, regularity.
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dc:
title
A Highly Regular and Scalable AES Hardware Architecture.
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52
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