A Multiple-Access Pipeline Architecture for Digital Signal Processing.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/McKinneyG88
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/tc/McKinneyG88
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dc:
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<
https://dblp.l3s.de/d2r/resource/authors/Brian_C._McKinney
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dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Fayez_El_Guibaly
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foaf:
homepage
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http://dx.doi.org/doi.org%2F10.1109%2F12.2165
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foaf:
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dc:
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DBLP journals/tc/McKinneyG88
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dc:
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DOI doi.org%2F10.1109%2F12.2165
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dcterms:
issued
1988
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swrc:
journal
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rdfs:
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A Multiple-Access Pipeline Architecture for Digital Signal Processing.
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foaf:
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<
https://dblp.l3s.de/d2r/resource/authors/Brian_C._McKinney
>
foaf:
maker
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https://dblp.l3s.de/d2r/resource/authors/Fayez_El_Guibaly
>
swrc:
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3
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swrc:
pages
283-290
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http://bibsonomy.org/uri/bibtexkey/journals/tc/McKinneyG88/dblp
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rdfs:
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rdfs:
seeAlso
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https://doi.org/10.1109/12.2165
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dc:
subject
multiple-access pipeline architecture; digital signal processing; CMOS processor; processing concurrency; microprogram control; floating-point data; arithmetic logic unit; computerised signal processing; digital arithmetic; parallel architectures.
(xsd:string)
dc:
title
A Multiple-Access Pipeline Architecture for Digital Signal Processing.
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37
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