On Synthesis of Easily Testable (k, K) Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/tc/NaiduC03
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http://dblp.uni-trier.de/rec/bibtex/journals/tc/NaiduC03
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https://dblp.l3s.de/d2r/resource/authors/Srinath_R._Naidu
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https://dblp.l3s.de/d2r/resource/authors/Vijay_Chandru
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homepage
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http://dx.doi.org/doi.org%2F10.1109%2FTC.2003.1244946
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DBLP journals/tc/NaiduC03
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2003
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On Synthesis of Easily Testable (k, K) Circuits.
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https://dblp.l3s.de/d2r/resource/authors/Srinath_R._Naidu
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11
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1490-1494
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rdfs:
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dc:
subject
Testing, stuck-at fault, polynomial time, k-tree, treewidth, synthesis.
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dc:
title
On Synthesis of Easily Testable (k, K) Circuits.
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52
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